Normally, I try to not publish schoolwork on this site, mostly because the ideas for assigned projects come from the professor and not me. However, the final project for my Advanced VLSI Techniques class allows for students to present an original idea, so I feel that sharing this work is appropriate.
My idea is not exactly groundbreaking. Rather, I aim to provide a convenient tool for students studying different methods for decreasing power consumption in integrated devices. I call it RPRAC, which stands for RTL (Register Transfer Level) Power Reduction Approach Comparator. It's a program that applies one or several power reduction techniques to a provided logic design separately and measures and compares the effects that each technique has on power consumption, chip area, and signal timing.
Essentially, my plan for this program is to simply write a script that employs other VLSI design tools to do the actual heavy-lifting. As a student of a graduate VLSI course, I have access to machines with actual professional software suites, so I'm using ModelSim by Mentor Graphics for the Verilog testing and simulation, Synopsys Formality for functional verification, and Synopsys Design Compiler for netlist synthesis and measurement. A simple chart describing the general flow of the program is shown below:
I plan on implementing this in Python, which I've only used for mall experiments so far. Check out this GitHub page to check on the source. I might eventually post some wiki pages on there as well.